LCD has many advantages such as low working voltage, low power consumption, large amount of display information, long life, easy integration, easy portability, and low electromagnetic radiation pollution. It has emerged in display technology and is widely used in mobile phones, PDA products, and handheld instruments. Instruments and other portable electronic products and devices.
The LCD drive circuit is an important part of the liquid crystal display system and is an interface circuit between the computer (or MCU) and the liquid crystal panel. Its main function is to modulate the phase and peak value of the potential signal that is output to the electrodes of the liquid crystal display device. Frequency and other parameters to establish AC drive electric field. Due to the large difference in LCD specifications, the conventional method is to develop a dedicated drive circuit for each type of LCD. Such a design wastes time and has poor reusability. For this reason, it is necessary to design an IP core that can be used for most small-scale LCD drive circuits, and it is necessary to solve this problem by multiplexing the IP core. Currently, only Yu-Jung Huang and others from I-Shou University have designed IP cores that can drive LCDs of different sizes to achieve this function by embedding embedded microprocessors in the system. However, this embedded microprocessor makes the system more complex and more costly. The IP core of the drive circuit designed to drive the LCDs of different sizes is implemented using FPGA, which can effectively overcome the disadvantages of the circuit system complexity and high cost.
IP core system structure
Figure 1 IP core system structure
IP core cascade arrangement diagram
Figure 2 IP core cascade arrangement
Line control function simulation results
Figure 3 Row Control Function Simulation Results
Column control function simulation results
Figure 4 column control function simulation results
In order to meet the actual needs of most of today's smaller LCD display applications, the LCD driver circuit IP core chip designed in this paper has 64 COM (row) and 64 SEG (column) outputs, and has a high-speed 8-bit parallel MCU interface. And the serial interface, the chip contains the RAM that stores the display data, and has specially designed 10 control ends, can control conveniently and flexibly. It mainly has the following main functions:
1. Provide scan timing signal and display signal data for the liquid crystal display;
2, support the direct connection with the MCU in the form of a bus;
3, can drive different scales of LCD (n & TImes; m), n can be a continuous value (n = 0 ~ 63), m can only take a multiple of 8 (m = 8k, k take a natural number);
4. Supports the cascade between IP cores to drive larger LCDs, supporting up to 4 IP core inter-bank cascading and inter-column cascading;
5, can provide a wider range of drive output voltage to adapt to different LCD devices;
6, to provide picture-in-picture, split-screen display and other functions.
IP core design
In this paper, according to the "top-down" design method, first divide the chip into hierarchical functions, while referring to the existing LCD driver chip design experience, and combine the "bottom-up" design method to design some modules. Finally, According to the system design framework, each module is coordinated and the overall functional verification of the chip is performed so as to meet the requirements of the design specification.
The structure of the IP core system designed in this paper is shown in Figure 1. The IP core is mainly composed of the following modules: line scan and column signal driver module, level shifter, presettable number ring counter, data latch module, control logic module, display data RAM and address decode module, MCU Interface module. Some of these large modules can also be subdivided into several sub-modules.
Each module design
MCU interface module
The MCU interface module is an interface for communication between an IP core and an external controller (MCU) and is a channel for data transmission. The MCU writes commands, reads status, or displays data on the LCD driver chip through this interface. At the same time, the interface also accepts the command decoder control, so that read and write and internal operations combined. The chip is implemented by more complex internal combination logic and sequential logic circuits, which can be compatible with the two mainstream MCU control signals and support serial/parallel two data operation modes.
The module includes several sub-modules commonly used in the MCU interface module of the existing common LCD driving circuit, such as a data bus (8-bit) sub-module, a busy state detection sub-module, a read/write control sub-module, and an MCU release sub-module. A new row cascade and column cascade control submodule has been added. The data bus is mainly used for internal and external data exchanges; the busy status detection submodule is used to determine the status of the MCU, generates a system busy signal to coordinate signal read and write operations and receive internal/external reset signals; the read and write control submodule is used to generate correct The read-write control sequence; MCU release sub-module function is through logic combination, in the chip to perform the "read-modify-write" process, release the MCU so that the MCU can perform other operations at the same time; and the new cascade controller The main function of the module is to achieve row concatenation and column concatenation between IP cores. Up to 16 IP concatenations (4 rows and 4 ranks each) can be supported. CS0~CS1 are cascade control ports, and CS2~CS3 are column levels. Joint control. For example, assume that there is an LCD (128 & TImes; 256), which can be driven by 8 IP cores. When the settings are made, the CS is 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, which can constitute 2 & TImes; Drive the IP core array. The schematic diagram of its arrangement is shown in Figure 2.
Display data RAM and address decoding module
This module is mainly used to store the data to be displayed, and acts as a buffer between the MCU interface and the signal driver circuit to ensure the stable output of the display data.
The module includes two sub-modules: a RAM array and an address decoder for storing display data. First, the column address is provided by the column address circuit, a column of 8-bit RAM memory cells is selected by the column address decoder, and the MCU reads/writes through the interface; then, the row address decoder scans the RAM in units of rows. In combination with the display data latch circuit, the entire row of data can be output and output to the liquid crystal display for display by the electrode driving circuit.
Data latch module
The module contains two sub-modules: the column number control latch sub-module and the drive latch sub-module. The column number control latch submodule is composed of k parallel 8-bit data latches. The main function is to latch the data on the data bus and output it from the RAM to the RAM under the control signal and clock signal of the control logic module. The display data signals on the bit data bus are respectively latched in the corresponding 8-bit data latches. The 64-bit data requires 8 times and 8 bits each time. The driver latch sub-module is a 64-bit drive latch formed by 64 1-bit latches connected in parallel. Its role is to put the upper 8 8-bit data under the control signal and clock signal of the control logic module. The m-bit data transmitted in the latch is latched all at once, and then input to the column signal electrode driver module.
Control logic module
The main role of this module is to control signal data transmission and select the number of column signal lines. The column number control latch sub-module, the drive latch sub-module, and the clock generator can be controlled by the column number control input M to achieve the functions applicable to different sizes of LCDs. According to needs, by inputting different values to the column number control input M, it controls how many bit number control latches are in the working state, and the other latch units are set to the idle state. The data in the display data RAM is latched into the corresponding column number control latch through the 8-bit data bus during the duty cycle, and then latched into the drive latch for the electrode drive at a time under the control of a clock signal. Module input signal. In this way, the IP core can implement the function of controlling the number of selected columns. When M is "000", the lower 8 bits (first latch) of the column number control latch operate, and the other is all idle, and the corresponding column electrodes are SEG0~SEG7; when M is "001" The lower 16 bits (first and second latches) of the column control latch operate. All other columns are free. The corresponding column electrodes are SEG0~SEG15; and so on, until the column control latches 64. Bit register all work, the corresponding column electrode is SEG0 ~ SEG63.
Electrode drive module
The module mainly includes four sub-modules: a row scan electrode driving sub-module, a column signal electrode driving sub-module, a level shifter, and a preset number ring counter.
The function of the level shifter is to convert the voltage of the logic signal into an actual LCD driving voltage by an applied control signal and output to the driving module according to the actual application needs; the role of the row scanning electrode driving sub module is to provide the row electrodes with A certain period of the scanning signal pulse; the function of the column signal electrode driving sub-module is to apply the data from the latch to the corresponding column electrode, and the scanning signal of the row electrode to establish the AC driving electric field, thereby driving the display of the LCD device. The number of ring counters that can be preset can control the number of row scanning electrodes through the row number control terminal N (S0~S5) to adapt to LCD screens of different sizes, and input different values to the row number control terminal N according to actual needs. Control the number of rows for a specific job and all other electrodes are idle. Under the control of the line drive clock signal, scanning is performed line by line, and the cycle is repeated until a new value is input to the line number control terminal N, and a new line number of line electrodes is scanned in a line-by-line manner. For example, when the applied signal N is “011011”, the number of scanning electrodes is 27. The row scan driving sub-module generates a progressive scan signal on the row electrodes COM0 COMCOM26, and the other row electrodes COM27 COMCOM63 are all set to a low level. If the new applied signal N is “100011”, the scan electrode driving sub-module generates a circulating progressive scan signal on the row electrodes COM0 COMCOM34.
IP core system implementation
First, according to the above definition and division of the entire system function and the design of each module, each function module is separately modeled by VHDL language; secondly, on the Xilinx company's FPGA device, the EDA tool ISE is used for simulation and synthesis. Debug and optimize the design; then, use VHDL to define the top-level module to connect each module and perform corresponding system debugging and verification; finally, get a LCD driver circuit with 64 COM (rows) and 64 SEGs (columns) Output, high-speed 8-bit parallel MCU interface and serial interface, the chip contains RAM for display data, and can be cascaded to control the CS to expand the cascade to meet the larger LCD, through the column number control M and the number of rows control terminal N to adapt to different sizes of LCD.
Simulation and verification
This article uses Xilinx simulation software ISE as a simulation tool to verify the designed IP core in two steps.
First, this paper first performs preliminary functional verification of each module of the IP core (including internal sub-modules). Then, referring to the working process of the chip, the entire chip is simulated as a whole. Figures 3 and 4 show simulation results using ISE to simulate the row and column control functions of the entire IP core. In the figure, CLK and CLK1 are the data transmission control clocks and row electrode scan pulses of the MCU interface module, respectively; M and N are the selection control terminals for the column and row electrodes, respectively; the low two and high two bits of CS are cascaded respectively. Cascade control ends with columns.
The simulation results in Figure 3 and Figure 4 illustrate:
1. When RESET is high, IP core is in the initial state or clear state; when WRITE is high, IP core is in working state and can receive display data.
2. On the rising edge of the clock CLK, the MCU writes 8-bit display data to the IP core's RAM in parallel through the interface; on the rising edge of the clock CLK1, the horizontal scan driving electrodes sequentially output the scan pulses, and the column signal electrodes will put the data in the RAM. Output from SEG.
3. The number of rows of control terminals can change the number of rows of electrodes scanned. When the row number selection control terminal N is "3E", a scan signal is output at COM0~COM61. As shown in FIG. 3, in the first row clock signal, the scanning signal is output on the electrode COM61, and the row electrode is scanned row by row under the control of the row driving clock; when the seventh row clock signal is entered, N becomes “ 22", the scanning signal is output on the row electrode COM33, and progressively decremented. The progressive scanning of COM0~COM33 is performed.
4. The column number control terminal can change the number of electrodes of the column signal. When the column number selection control terminal M is "110", the SEG electrode is a 48-bit output; when M is "010", the output of the SEG becomes 16 bits; when M is "101", the output of the SEG becomes 40 bits. ; When M is "100", the output of the SEG becomes 32 bits.
In this paper, the functions of column number control, row number control, and inter-core cascading of the IP core have been functionally verified and verified. The limited space here only describes the column number and row number control functions.
This paper discusses the design of an LCD display driver chip IP core. According to the top-down design idea, the chip is divided into layers and the overall function of the chip is verified. In the functional verification of the chip, this paper adopts VHDL hardware description language to verify the logic function and timing relationship of the circuit. The LCD display driver adopts a parametric design and has a good portability, and can be conveniently applied to various flat panel display system applications of portable instruments and PDAs and other related products.